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DSIM UVM Test Workflow

dsim-workflow

DSIM UVM test execution workflow using PowerShell scripts. Use when compiling tests, running simulations, executing regression suites, or troubleshooting DSIM issues.

SKILL.md

Full skill instructions

DSIM UVM Test Workflow

PowerShell script-based workflow for the AXIUART_RV32I verification environment.

When to Use This Skill

  • Compiling or running UVM tests
  • Executing regression test suites
  • Troubleshooting DSIM environment issues
  • Understanding VS Code task integration

Primary Workflow (MANDATORY)

Use PowerShell scripts in scripts/

ScriptPurpose
run_test.ps1Single test execution
run_regression.ps1Batch test execution

Note: MCP-based execution has been deprecated. The deprecated_mcp_server/ directory is retained for reference only.

Standard UVM Test Sequence

1. Run Single Test

.\scripts\run_test.ps1 <test_name> [-Verbosity <level>] [-Waves] [-Seed <n>]

Examples:

# Basic test execution
.\scripts\run_test.ps1 vexriscv_regfile_test

# With waveform capture
.\scripts\run_test.ps1 vexriscv_alu_test -Waves

# With higher verbosity
.\scripts\run_test.ps1 vexriscv_pipeline_flow_test -Verbosity UVM_MEDIUM

2. Run Regression Suite

.\scripts\run_regression.ps1 [-Stage <n>] [-Tests <list>] [-Verbosity <level>] [-Waves] [-StopOnFail]

Examples:

# Run all Stage 1 tests
.\scripts\run_regression.ps1 -Stage 1

# Run specific tests
.\scripts\run_regression.ps1 -Tests vexriscv_regfile_test,vexriscv_alu_test

# Stop on first failure
.\scripts\run_regression.ps1 -Stage 1 -StopOnFail

Available Tests (Stage 1)

Test NamePurpose
vexriscv_regfile_testRegister file read/​write
vexriscv_alu_testALU operations
vexriscv_pipeline_flow_testPipeline instruction flow
vexriscv_ibus_fetch_testInstruction bus fetching
vexriscv_memory_access_testLoad/​Store operations
vexriscv_ex_bypass_testEX stage forwarding
vexriscv_mem_bypass_testMEM stage forwarding
vexriscv_wb_bypass_testWB stage forwarding
vexriscv_load_use_stall_testLoad-use hazard stall
vexriscv_dbus_access_testData bus access

Script Parameters

run_test.ps1

ParameterTypeDefaultDescription
-TestNamestring(required)UVM test class name
-VerbosityenumUVM_LOWUVM_LOW, UVM_MEDIUM, UVM_HIGH, UVM_DEBUG
-WavesswitchfalseEnable waveform capture (.mxd)
-Seedint1Random seed
-CompileOnlyswitchfalseCompile without running
-RunOnlyswitchfalseRun using existing compiled image

run_regression.ps1

ParameterTypeDefaultDescription
-Stageint0Run tests for specific stage (1, 2, etc.)
-Testsstring[]@()Comma-separated list of specific tests
-VerbosityenumUVM_LOWUVM verbosity level
-WavesswitchfalseEnable waveform capture for all tests
-StopOnFailswitchfalseStop regression on first failure
-ReportFilestringautoCustom report file path

VS Code Task Integration

Use VS Code tasks from the Command Palette (Ctrl+Shift+P > "Tasks: Run Task"):

TaskDescription
DSIM: Run Single TestRun selected test with chosen verbosity
DSIM: Run Single Test with WavesRun with waveform capture
DSIM: Run Stage 1 RegressionRun all Stage 1 tests
DSIM: Run Selected TestsRun comma-separated test list
DSIM: Run regfile_testQuick access to regfile test
DSIM: Run alu_testQuick access to ALU test

Output Locations

Output TypeLocation
Test logssim/​exec/​logs/<test_name>_<timestamp>.log
Result JSONsim/​exec/​logs/<test_name>_<timestamp>_result.json
Waveformssim/​exec/​wave/<test_name>_<timestamp>.mxd
Regression reportsim/​exec/​logs/​regression_<timestamp>.txt
Regression JSONsim/​exec/​logs/​regression_<timestamp>.json

Result JSON Format

Single Test Result

{
  "test_name": "vexriscv_regfile_test",
  "status": "success",
  "exit_code": 0,
  "log_file": "sim/​exec/​logs/​vexriscv_regfile_test_20260131_111315.log",
  "wave_file": "",
  "timestamp": "20260131_111315"
}

Regression Result

{
  "timestamp": "20260131_111114",
  "total_tests": 3,
  "passed": 3,
  "failed": 0,
  "skipped": 0,
  "status": "PASS",
  "results": {
    "vexriscv_regfile_test": "PASS",
    "vexriscv_alu_test": "PASS",
    "vexriscv_pipeline_flow_test": "PASS"
  }
}

Common Workflows

Quick Compile-Run Cycle

# Compile only
.\scripts\run_test.ps1 my_test -CompileOnly

# Run using compiled image
.\scripts\run_test.ps1 my_test -RunOnly

Debug with Waveforms

.\scripts\run_test.ps1 vexriscv_memory_access_test -Waves -Verbosity UVM_DEBUG

Full Stage 1 Regression

.\scripts\run_regression.ps1 -Stage 1 -Verbosity UVM_LOW

DSIM Environment

Scripts automatically configure DSIM environment:

  • DSIM_HOME: C:\Program Files\Altair\DSim\2025.1
  • License auto-discovery from standard locations
  • PATH includes DSIM binaries and dependencies

Environment Variables (Auto-configured)

VariableValue
DSIM_HOMEInstallation directory
DSIM_ROOTSame as DSIM_HOME
DSIM_LIB_PATHDSIM_HOME/​lib
DSIM_LICENSEAuto-discovered license file

Troubleshooting

DSIM Not Found

Verify DSIM installation:

Test-Path "C:\Program Files\Altair\DSim\2025.1\bin\dsim.exe"

License Issues

Check license file locations:

  • C:\Program Files\Altair\dsim-license.json
  • C:\Program Files\Altair\DSim\2025.1\dsim-license.json
  • $env:LOCALAPPDATA\metrics-ca\dsim-license.json

Test Not Found

Verify test exists in sim/​tests/ and is listed in sim/​uvm/​tb/​dsim_config.f.

Compilation Errors

See dsim-debugging skill for detailed troubleshooting.

Deprecated MCP Server

The MCP server has been deprecated. Files are retained in deprecated_mcp_server/ for reference only.

Do not use:

  • deprecated_mcp_server/​mcp_client.py
  • deprecated_mcp_server/​dsim_fastmcp_server.py
  • deprecated_mcp_server/​run_regression.py

Adding a New Test

Use add_test.ps1 to scaffold a new test. The script handles all registration automatically.

Command

.\scripts\add_test.ps1 -TestName <name> [-Description <desc>] [-Category <cat>] [-Stage <n>]

Parameters

ParameterValuesDescription
-TestName*_testTest class name (must end with _test)
-DescriptionstringPurpose of the test
-Categorysmoke, hazard, bus, memory, customTest classification
-Stage0, 10 = no stage, 1 = add to Stage 1 list
-TimeoutCyclesintCycle-based timeout (default: 200)
-ExpectedDurationSecintExpected run time in seconds

Examples

# New hazard test, added to Stage 1
.\scripts\add_test.ps1 -TestName vexriscv_branch_test `
    -Description "Branch instruction verification" `
    -Category hazard -Stage 1

# New custom test, not added to any stage
.\scripts\add_test.ps1 -TestName vexriscv_csr_test `
    -Description "CSR read/​write operations" `
    -Category custom

What the Script Does

The script modifies 4 files automatically:

FileAction
sim/​tests/<name>.svCreates test from template
sim/​uvm/​tb/​dsim_config.fAdds compilation entry
sim/​regression_tests.jsonAdds to regression suite
scripts/​run_regression.ps1Adds to stage list (if -Stage 1)

After Scaffolding

The generated test file (sim/​tests/<name>.sv) has two TODO sections to complete:

1. load_test_program() - Define the instruction sequence:

// Base address: 0x80000000 (program start)
// Data region:  0x80001000 (store/​load target, within 8KB BlockRAM)
write_memory_backdoor(32'h80000000, 32'h<encoding>);  // instruction
write_memory_backdoor(32'h80000004, 32'h00100073);    // EBREAK (halt)

2. verify_results() - Check register values:

read_cpu_reg(<reg_num>, reg_val);
if (reg_val != 32'h<expected>) begin
    `uvm_error(get_type_name(),
        $sformatf("FAIL: x%0d = 0x%08X (expected 0x%08X)", <n>, reg_val, <expected>))
    all_pass = 0;
end

Memory Map Reference

BlockRAM: 0x80000000 - 0x80001FFF (8KB total)
  Program: 0x80000000 - 0x800001FF (128 instructions max)
  Data:    0x80001000 - 0x80001FFF (store/​load target)

RV32I Encoding Quick Reference

InstructionFormatEncoding
ADDI rd, rs1, immI-typeimm[11:0]|rs1[4:0]|000|rd[4:0]|0010011
LUI rd, immU-typeimm[31:12]|rd[4:0]|0110111
SW rs2, off(rs1)S-typeimm[11:5]|rs2[4:0]|rs1[4:0]|010|imm[4:0]|0100011
LW rd, off(rs1)I-typeimm[11:0]|rs1[4:0]|010|rd[4:0]|0000011
EBREAK-0x00100073
NOP-0x00000013

Register encoding: x0=0, x1=1, ..., x15=0xF, x31=0x1F

Full Workflow

1. Scaffold     .\scripts\add_test.ps1 -TestName my_test -Category smoke -Stage 1
2. Edit         sim/​tests/​my_test.sv  (define sequence + checks)
3. Test         .\scripts\run_test.ps1 my_test -Waves -Verbosity UVM_MEDIUM
4. Debug        Open sim/​exec/​wave/​my_test_*.mxd (if failures)
5. Regression   .\scripts\run_regression.ps1 -Stage 1

Summary

Workflow principles:

  1. Use PowerShell scripts in scripts/ (mandatory)
  2. Standard sequence: run_test.ps1 for single tests, run_regression.ps1 for batch
  3. New tests: add_test.ps1 scaffolds and registers automatically
  4. Use VS Code tasks for common operations
  5. Consume JSON outputs from sim/​exec/​logs/
  6. Check waveforms in sim/​exec/​wave/ when debugging
  7. See dsim-debugging skill for troubleshooting

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