de10nano-mac-accelerator

DE10-Nano MAC Accelerator — FPGA + HPS Dot-Product Engine

A complete FPGA accelerator project for the Terasic DE10-Nano (Intel Cyclone V SoC) that implements a 16-unit parallel MAC (Multiply-Accumulate) array with DMA-based DDR3 data movement, controlled from Linux via memory-mapped registers.

System Architecture

┌─────────────────────┐          ┌─────────────────────────────┐
│   HPS (ARM Cortex-A9)│          │      FPGA Fabric            │
│                     │          │                             │
│  Linux + C program  │  LW H2F  │  ┌───────────────────────┐  │
│  mmap(/dev/mem)  ───┼──Bridge──┼──┤   mac_accelerator     │  │
│                     │          │  │  Registers + FSM +     │  │
│  DDR3 (1GB)         │ F2SDRAM  │  │  DMA + 16× MAC +      │  │
│  A[], B[] vectors ◄─┼──Bridge──┼──┤  BRAM + Reduce Tree   │  │
│                     │          │  └───────────────────────┘  │
└─────────────────────┘          └─────────────────────────────┘

Features

• 16 parallel MAC units using Cyclone V DSP blocks (scalable to 48)
• Burst DMA engine for efficient DDR3 data movement via F2SDRAM bridge
• Dual BRAM buffers for active working data (1-cycle access)
• Pipelined reduction tree (log₂(16) = 4 stages)
• Memory-mapped CSR registers for HPS control via Lightweight bridge
• 64-bit accumulation to prevent overflow on large vectors
• Performance counters for profiling
• Complete HPS C driver with mmap-based register access
• Parameterized design — change NUM_MACS and everything adapts
• Ready to evolve toward CSR/sparse matrix processing

File Structure

├── rtl/
│   ├── mac_unit.v              — Single MAC: multiply + accumulate (DSP inference)
│   ├── mac_array.v             — Parameterized array of N MAC units
│   ├── reduction_tree.v        — Pipelined adder tree for partial sum reduction
│   ├── bram_buffer.v           — Dual-port BRAM wrapper (M10K inference)
│   ├── accel_csr.v             — Avalon-MM slave: control/status register file
│   ├── accel_dma.v             — Avalon-MM master: DDR3 burst read/write engine
│   ├── accel_fsm.v             — Master FSM: orchestrates fetch→compute→reduce
│   ├── mac_accelerator.v       — Top accelerator module (Platform Designer component)
│   ├── de10nano_top.v          — Board top-level: HPS + accelerator
│   └── tb_mac_accelerator.v    — Full testbench with mock DDR3
├── sw/
│   ├── accel_driver.h          — Register map + inline helper functions
│   ├── accel_test.c            — HPS test program with verification & benchmarking
│   └── Makefile                — Cross-compile for ARM Cortex-A9
├── qsys/
│   ├── mac_accelerator_hw.tcl  — Platform Designer component description
│   └── soc_system_setup.md     — Step-by-step Qsys configuration guide
├── scripts/
│   ├── pin_assignments.tcl     — DE10-Nano FPGA pin assignments
│   ├── de10nano_accel.sdc      — Timing constraints (50 MHz)
│   └── program_fpga.sh         — Program FPGA from Linux
└── docs/
    ├── 00_ARCHITECTURE.md      — Full system architecture + dataflow
    ├── 01_QUARTUS_FLOW.md      — Complete build instructions
    └── 02_SCALING.md           — Scaling guide: more MACs, CSR/sparse

Register Map

Quick Start

1. Set up Quartus 18.1 project with device 5CSEBA6U23I7
2. Configure Platform Designer following qsys/soc_system_setup.md
3. Compile and generate .rbf file
4. Cross-compile sw/accel_test.c for ARM
5. Program FPGA and run test — see docs/01_QUARTUS_FLOW.md

Scaling

Change one parameter to scale:

parameter NUM_MACS = 32   // in mac_accelerator.v

Everything adapts automatically. See docs/02_SCALING.md for CSR/sparse roadmap.

Resource Usage (16 MACs at 50 MHz)

License

MIT