hrm-chip-router-7m

HRM Chip Router: 7M Parameter Hierarchical Reasoning Model

The Brown Forces 7M HRM Chip Router is a research release of a Hierarchical Reasoning Model (HRM) trained to solve multi-net, multi-layer 3D chip routing problems. This model routes complex 3D grids in under 2 seconds on consumer hardware, demonstrating the power of recursive reasoning in electronic design automation (EDA).

🔧 Try it live — no Cadence license required

This is the open research release. The production-grade routing platform is launching at route.brownforces.io — built on this architecture, optimized for real silicon designs (ibex, riscv32i, aes, jpeg-class and beyond). No $100k EDA license.

→ Join the waitlist at brownforces.io/chip-router

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Key Performance Metrics

• Fine-Tuned Full-Puzzle Connectivity: 13.09% — a +319% explosion over the imitation learning baseline (production model, actively improving)
• Token Accuracy: 97.9% (3D spatial geometry fully transfers)
• Zero-Shot Transfer (ibex topology): 87.6% connected, 0 obstacle violations
• Zero-Shot Transfer (riscv32i topology): 65.1% connected, 0 obstacle violations
• Imitation Learning Baseline (this checkpoint): 3.53% full-puzzle connectivity
• Connectivity Solved-Rate (Per Net): ~25% (symmetrical across all 4 nets)
• Inference Speed: ~2 seconds per 64-puzzle batch (RTX 5090)
• Model Size: 27.3M physical parameters (verified by direct parameter audit), 105 MB checkpoint — named HRM-7M following the original Samsung SAIL paper's model designation, not the physical count

Note: The fine-tuned connectivity figure above reflects the production model available at route.brownforces.io. This open-source checkpoint (step_60764) is the imitation learning baseline at 3.53%.

Methodology note: All connectivity solve-rates are measured on a held-out test set of routable puzzles generated by a classical A* router. A* defines the solvable distribution — every test puzzle has at least one valid routing (A* solves 100% by construction). Reported solve-rates are the fraction of these A*-solvable puzzles the model also routes. The train/test split is frozen and disjoint.

Architecture

The model uses a Hierarchical Reasoning Model (HRM) architecture with Adaptive Computation Time (ACT) halting. It operates on a 16×4×16 3D grid with a vocabulary of 7 tokens.

• Input Grid: 16x4x16 (Row x Layer x Column)
• Vocabulary: 7 tokens (0=pad, 1=empty, 2=obstacle, 3-6=net colors 0-3)
• Reasoning Steps: 16 ACT steps per inference

Usage

For full implementation and evaluation code, visit the GitHub repository.

Quick Inference

import torch
from evaluate_checkpoints import load_model_for_checkpoint, run_inference

# Load the 7M model (requires CUDA)
model, ds, meta = load_model_for_checkpoint("checkpoints/step_60764")
inputs, preds = run_inference(model, ds, meta, max_batches=1)

print(f"Routed {len(preds)} puzzles.")

Citation

@article{trm2025,
  title={TinyRecursiveModels: Reasoning through Recursion},
  author={Samsung SAIL Montreal},
  journal={arXiv preprint arXiv:2510.04871},
  year={2025}
}

@misc{hrm_chip_router_2026,
  author = {Brown Forces Technology Studio Inc.},
  title = {HRM Chip Router: 7M Parameter Hierarchical Reasoning Model},
  year = {2026},
  publisher = {GitHub},
  journal = {GitHub repository},
  howpublished = {\url{https://github.com/Brown-Forces-Technology-Studio-Inc/hrm-chip-router}}
}