ChiseLLM-7B

ChiseLLM Models

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GitHub

ChiseLLM is a series of large reasoning models specifically trained for the Chisel Hardware Construction language, aimed at revolutionizing HCL-Baed Agile Hardware Development Methodology (AHDM).

Built on Qwen/Qwen2.5-Coder-Instruct with domain-adaptive fine-tuning, the model combines high-quality reasoning datasets and specific thinking patterns to significantly enhance performance in hardware design tasks.

ChiseLLM Models can:

• Transform natural language specifications into high-quality Chisel code (Spec-to-Chisel)
• Intelligently translate Verilog code into enhanced Chisel implementations (Decompile-to-Chisel)
• Generate hardware designs with superior variability and extensibility, surpassing traditional design approaches

Use Cases

ChiseLLM Models is particularly suited for the following applications:

• Rapid Hardware Design Prototyping: Dramatically shortens the design cycle from specification to implementation
• Verilog Code Modernization: Intelligently converts legacy Verilog code into extensible Chisel implementations
• Hardware Architecture Exploration: Generates multiple design variants for the same functional requirements
• Design Refactoring and Optimization: Leverages Chisel's advanced features to improve existing hardware designs
• Agile Hardware Development Education: Serves as an assistive tool for learning Chisel and modern hardware design methods

Training results

Spec-to-Chisel task on VerilogEval:

Decompile-to-Chisel task on VerilogEval:

Framework versions

• Transformers 4.51.0
• Pytorch 2.6.0a0+df5bbc09d1.nv24.12
• Datasets 3.4.1
• Tokenizers 0.21.0

Training hyperparameters

The following hyperparameters were used during training:

• learning_rate: 1e-05
• train_batch_size: 2
• eval_batch_size: 8
• seed: 42
• distributed_type: multi-GPU
• num_devices: 8
• gradient_accumulation_steps: 8
• total_train_batch_size: 128
• total_eval_batch_size: 64
• optimizer: Use OptimizerNames.ADAMW_TORCH with betas=(0.9,0.999) and epsilon=1e-08
• lr_scheduler_type: cosine
• lr_scheduler_warmup_ratio: 0.05
• num_epochs: 3.0

Citation

If you are interested in our work, please consider citing this, it would be greatly appreciated!

@misc{wang2025chisellmunleashingpowerreasoning,
      title={ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development}, 
      author={Bowei Wang and Jiaran Gao and Yelai Feng and Renzhi Chen and Shanshan Li and Lei Wang},
      year={2025},
      eprint={2504.19144},
      archivePrefix={arXiv},
      primaryClass={cs.AI},
      url={https://arxiv.org/abs/2504.19144}, 
}