TwinLiteNet-LiteRT

Measured on device (edge-compat): Raspberry Pi 5 · LiteRT 2.2.0.dev20260804 · CPU/XNNPACK, 4 threads · 261 ms p50 (2026-08-31); browser · Chromium 151 on M4 Max · LiteRT.js 2.5.3 · WebGPU · 19.3 ms p50 · output differs from CPU (max rel diff 0.005) (2026-08-11). Record: https://github.com/john-rocky/edge-compat/blob/main/cards/twinlitenet/CARD.md

TwinLiteNet — Drivable-area + lane segmentation (LiteRT GPU)

On-device drivable-area and lane-line segmentation running fully on the LiteRT CompiledModel GPU delegate (no CPU fallback). TwinLiteNet (2023) is an ultra-light ESPNet-based network with two segmentation heads — the ADAS perception building block "where can I drive" + "where are the lanes". Only 3.1 MB, ~44 ms/frame on a Pixel 8a.

• Architecture: ESPNet-C encoder + two seg decoders — pure CNN.
• Weights: chequanghuy/TwinLiteNet (BDD100K) · MIT.
• Size: 3.1 MB.

Drivable area (green) + lane lines (red) on a dashcam highway frame. Source: Wikimedia Commons (Public Domain).

I/O

• Input: [1, 3, 360, 640] NCHW, RGB, x/255.
• Outputs: two [1, 2, 360, 640] logit maps — drivable_area and lane_line. Take argmax over the class dim (2) → binary masks.

GPU conversion

TwinLiteNet is a pure CNN. It converts fully GPU-compatible (270/270 nodes on the delegate, 1 partition; device corr 0.99997 / 0.99998 on the two heads, ~44 ms) with one patch: the ConvTranspose2d upsamplers → ZeroStuffConvT2d (nearest-upsample

• stride zero-stuff mask + flipped conv; the Mali delegate rejects TRANSPOSE_CONV). Exact. CPU-exact vs PyTorch (corr 1.0).

Minimal usage

Kotlin (Android, LiteRT CompiledModel GPU)

val options = CompiledModel.Options(Accelerator.GPU)
val model = CompiledModel.create(context.assets, "twinlite.tflite", options, null)
val inBufs = model.createInputBuffers()
val outBufs = model.createOutputBuffers()   // [0] = drivable area, [1] = lane line

inBufs[0].writeFloat(inputNCHW)             // [1,3,360,640] RGB, x/255
model.run(inBufs, outBufs)
val da = outBufs[0].readFloat()             // [2*360*640]; argmax over the 2 classes -> drivable mask
val ll = outBufs[1].readFloat()             // [2*360*640]; argmax -> lane mask
// per pixel p: class = if (da[p] > da[360*640 + p]) 0 else 1

Python (LiteRT / ai-edge-litert)

import numpy as np
from ai_edge_litert.interpreter import Interpreter

it = Interpreter(model_path="twinlite.tflite"); it.allocate_tensors()
inp, out = it.get_input_details(), it.get_output_details()
it.set_tensor(inp[0]["index"], x)           # [1,3,360,640] float32, RGB, x/255
it.invoke()
outs = sorted(out, key=lambda o: o["index"])
da = it.get_tensor(outs[0]["index"])[0].argmax(0)   # [360,640] drivable-area mask
ll = it.get_tensor(outs[1]["index"])[0].argmax(0)   # [360,640] lane mask

Conversion

Converted with litert-torch (build_twinlite.py): loads the MIT BDD100K weights, swaps ConvTranspose2d → ZeroStuffConvT2d, and exports the two-head graph.

Performance

Measured on a Pixel 8a (Tensor G3, Android 16) with the standard TFLite benchmark_model tool — 10 warm-up runs then 50 timed runs, reported as the tool's mean.

The two GPU rows are different runtimes, not a contradiction. The LITERT_CL figure is the one recorded when this model shipped, taken through LiteRT's own CompiledModel accelerator — the path the Kotlin sample app and the LiteRT API use. The TfLiteGpuDelegateV2 figure is the classic TFLite OpenCL delegate, measured with a tool anyone can download and re-run. They agree on how much of the graph the GPU takes; they disagree on speed, and the classic delegate is the slower of the two here. Read the TfLiteGpuDelegateV2 row as a reproducible floor, not as this model's speed on LiteRT.

Snapdragon NPU (Hexagon)

This file runs on the Qualcomm Hexagon NPU as published — no conversion and no pre-compiled artifact. LiteRT compiles it on the device and caches the result.

Measured on a physical Samsung Galaxy S26 (Snapdragon 8 Elite Gen 5 / SM8850, Hexagon v81) with LiteRT CompiledModel 2.2.0 — 5 warm-up runs then 50 timed runs, one accelerator per process, every row taken at device thermal status NONE.

Inference is close to a tie (13.72 ms against 13.82 ms, 1.01x). The first launch pays once for on-device compilation; every launch after that loads in 121 ms against 1401 ms for the GPU (11.6x), because the GPU rebuilds its shaders each time. The file is fp16 and needs no int8 quantization to reach the NPU.

Running it on the NPU

Put these in jniLibs/arm64-v8a/. None of them are distributed from this repository — the first two come from Google, the rest from Qualcomm's own SDK:

Pick the runtime matching the device's Hexagon version: SM8550 → v73, SM8650 → v75, SM8750 → v79, SM8850 → v81.

val env = Environment.create(
    context,
    mapOf(
        Environment.Option.DispatchLibraryDir to context.applicationInfo.nativeLibraryDir,
        // Required for on-device compilation. Without it the model silently runs on CPU.
        Environment.Option.CompilerPluginLibraryDir to context.applicationInfo.nativeLibraryDir,
    ),
)
val options = CompiledModel.Options(Accelerator.NPU).apply {
    qualcommOptions = CompiledModel.QualcommOptions(
        htpPerformanceMode = CompiledModel.QualcommOptions.HtpPerformanceMode.BURST
    )
}
val model = CompiledModel.create(context.assets, "twinlite.tflite", options, env)

Build settings: useLegacyPackaging = true under packaging { jniLibs { … } }, so the DSP can open the skel from a real path, and Kotlin 2.3+ for LiteRT 2.2.0's metadata.

Every NPU failure here is silent. There is no error when the NPU is unavailable — you get a plausible CPU number instead. Confirm from logcat which delegate took the graph: Replacing 1 out of 1 node(s) with delegate (DispatchDelegate) is the NPU, while ... (TfLiteXNNPackDelegate) is the CPU. A missing library is reported only as a W-level dlopen failed line under a generic No compiler plugin found summary.

On the conditions. Thermal headroom is reported as measured, where 1.0 is the throttling threshold. All rows were taken at a comparable headroom and compare directly; figures taken at a different headroom will differ. Each accelerator ran in its own process, because LiteRT's Environment is shared within one and the first model load fixes the options for every later one.

Raspberry Pi 5 (CPU)

Measured on a Raspberry Pi 5 Model B Rev 1.1 (8 GB, Raspberry Pi OS 64-bit) with the LiteRT benchmark_model tool from litert-cli-nightly 0.2.0.dev20260805: CPU inference (XNNPACK, 4 threads), 3 invocations per file of 10 warm-up plus 50 timed runs (the tool caps a phase at 150 s, so very slow graphs run fewer — the Runs column is the actual timed total). The latency is the median across invocations; the spread is the min–max over all timed runs. No thermal throttling occurred during these runs (vcgencmd get_throttled stayed 0x0).

License

MIT (TwinLiteNet / chequanghuy). Trained on BDD100K.