PCB-AOI-Hardware-Constraint

PCB AOI Hardware Constraint

Overview

This project focuses on PCB (Printed Circuit Board) defect detection using deep learning, with an emphasis on deploying the model on hardware-constrained edge devices.

The main objective is to take a trained YOLO object detection model and optimize it for deployment on devices with limited computational resources, such as a Raspberry Pi or other CPU-based edge devices.

The project contains both the original trained model and an optimized INT8 ONNX model.

The overall pipeline is:

                    PCB Image
                        |
                        v
                  Image Input
                        |
                        v
                 SAHI Slicing
                        |
             +----------+----------+
             |          |          |
             v          v          v
          Slice 1    Slice 2    Slice 3
             |          |          |
             +----------+----------+
                        |
                        v
                 INT8 ONNX Model
                        |
                        v
                 Object Detection
                        |
                        v
                Detection Merging
                        |
                        v
                 Final Results

---

Motivation

PCB Automated Optical Inspection (AOI) requires detecting manufacturing defects from PCB images.

In a conventional setup, a deep learning model can be executed on a powerful GPU. However, deploying the same model on an edge device introduces several hardware limitations.

Typical edge devices may have:

• Limited RAM
• Limited CPU performance
• Limited storage
• Limited power
• No dedicated GPU

Therefore, simply training a model is not enough. The model also needs to be optimized for the hardware on which it will eventually run.

This project explores the following approach:

Trained YOLO Model
        |
        v
INT8 Quantization
        |
        v
ONNX Model
        |
        v
CPU / Edge Device
        |
        v
PCB Defect Detection

---

Why INT8 Quantization?

Deep learning models normally use floating-point numbers such as FP32 for storing weights and performing calculations.

For example:

FP32
32 bits per value

INT8 uses:

INT8
8 bits per value

Reducing the numerical precision can significantly reduce the amount of memory required to store the model.

It can also reduce the amount of data that needs to be moved during inference and can improve inference efficiency on hardware that supports INT8 operations.

The main advantages are:

• Smaller model size
• Lower memory requirements
• Lower storage requirements
• Reduced memory bandwidth requirements
• Potentially faster CPU inference
• Better suitability for embedded devices

The main trade-off is that quantization can introduce some loss in model accuracy.

Therefore, the INT8 model should always be evaluated against the original FP32 model to determine the accuracy/speed trade-off.

---

Model Optimization

The original trained YOLO model is provided as:

best.pt

The optimized model is provided as:

best_int8.onnx

The approximate model sizes are:

The INT8 ONNX model is approximately 50% smaller than the original model.

This reduction is particularly useful for edge deployment where storage and memory are limited.

---

Why ONNX?

The original model is stored in PyTorch/Ultralytics format.

Although this format is convenient for training and development, it is not always the most suitable format for deployment on different hardware platforms.

ONNX provides a hardware-independent model representation that can be executed using inference runtimes such as ONNX Runtime.

The deployment flow is therefore:

PyTorch / Ultralytics Model
            |
            v
       ONNX Export
            |
            v
     INT8 Quantization
            |
            v
     INT8 ONNX Model
            |
            v
      ONNX Runtime
            |
            v
       Edge Device

This makes the optimized model easier to integrate into CPU-based and embedded inference pipelines.

---

Why SAHI?

PCB defects can be extremely small compared with the complete PCB image.

For example, suppose the original PCB image is very large:

Large PCB Image
       |
       v
     Resize
       |
       v
640 x 640

A very small defect in the original image may occupy only a few pixels after resizing.

This can make small defects difficult to detect.

To address this problem, this project uses SAHI (Slicing Aided Hyper Inference).

Instead of only processing the entire PCB image, SAHI divides the image into smaller overlapping slices.

For example:

+----------------+----------------+----------------+
|                |                |                |
|    Slice 1     |    Slice 2     |    Slice 3     |
|                |                |                |
+----------------+----------------+----------------+
|                |                |                |
|    Slice 4     |    Slice 5     |    Slice 6     |
|                |                |                |
+----------------+----------------+----------------+

Each slice is passed through the object detection model independently.

The detections from all slices are then merged.

This allows the model to effectively operate on smaller regions of the PCB image and can improve the detection of small defects.

---

SAHI Configuration

The current inference pipeline uses:

Slice Size       : 512 x 512
Slice Overlap    : 20%
Post Processing  : GREEDYNMM
Match Metric     : IOS
Match Threshold  : 0.5

The overlap between slices is important because a defect may lie near the boundary of two slices.

Without overlap:

+----------+----------+
|          |          |
|          | defect   |
|          |    |     |
+----------+----------+

The defect could be split between two slices.

With overlap:

+---------------+
|       +-------+-------+
|       |       |       |
|       | defect|       |
+-------+-------+       |
        |               |
        +---------------+

The same defect can therefore be captured more completely by at least one of the slices.

---

Complete Inference Pipeline

The hardware-oriented inference pipeline is:

                 Input PCB Image
                        |
                        v
                 Image Processing
                        |
                        v
                   SAHI Slicing
                        |
                        v
          +-------------+-------------+
          |             |             |
          v             v             v
       Slice 1       Slice 2       Slice N
          |             |             |
          +-------------+-------------+
                        |
                        v
                INT8 ONNX YOLO
                        |
                        v
                Object Detection
                        |
                        v
               Detection Results
                        |
                        v
                SAHI Postprocess
                        |
                        v
                Merge Detections
                        |
                        v
                Final Predictions

---

Repository Contents

---

Original Model

The original trained model is:

best.pt

Approximate size:

20.3 MB

This model represents the original trained model before conversion to the optimized INT8 ONNX format.

It can be used during development and testing with the Ultralytics framework.

---

INT8 ONNX Model

The optimized model is:

best_int8.onnx

Approximate size:

10.1 MB

This model is intended primarily for deployment on CPU-based and edge hardware.

The reduced model size makes it more suitable for environments where RAM and storage are limited.

---

Model Export

The model can be exported to ONNX using the following approach:

from ultralytics import YOLO

model = YOLO("best.pt")

model.export(
    format="onnx",
    imgsz=640,
    quantize=8,
    data="data.yaml",
    split="val",
    fraction=1.0,
    dynamic=False,
    simplify=True,
    device="cpu"
)

The important export parameters are:

Image Size      : 640 x 640
Quantization    : INT8
Format          : ONNX
Dynamic Shape   : Disabled
Simplification  : Enabled
Device          : CPU

---

Installation

Install the required Python packages:

pip install ultralytics
pip install sahi
pip install opencv-python
pip install onnx
pip install onnxruntime

---

Running the Original Model

The original model can be tested using:

detect.py

Set the model and image paths in the script:

MODEL_PATH = "best.pt"
IMAGE_PATH = "test.jpg"

Then run:

python detect.py

The script performs object detection using the original model together with the SAHI pipeline.

---

Running the INT8 Model

The INT8 ONNX model can be tested using:

detect1.py

Set:

MODEL_PATH = "best_int8.onnx"
IMAGE_PATH = "test.jpg"

Then run:

python detect1.py

The INT8 model is intended to run on CPU and does not require a dedicated GPU.

---

Confidence Threshold

The INT8 inference pipeline currently uses a confidence threshold of:

0.35

This means predictions below the selected confidence threshold are filtered out.

The threshold can be adjusted depending on the application.

For example:

CONFIDENCE_THRESHOLD = 0.35

A lower threshold may detect more potential defects but can also increase false positives.

A higher threshold may reduce false positives but can cause some lower-confidence defects to be missed.

Therefore, the appropriate value should be determined experimentally using the target dataset.

---

FP32 vs INT8

The two available models serve different purposes.

The INT8 model provides a substantially smaller model footprint.

However, model size alone does not determine real-world performance.

The actual benefit should be measured using:

• Inference latency
• FPS
• RAM usage
• CPU utilization
• Power consumption
• Detection accuracy

on the target hardware.

---

Hardware-Constrained Deployment

The main purpose of this project is to investigate how a PCB defect detection model can be deployed on hardware with limited resources.

A possible deployment target is a Raspberry Pi.

The conceptual deployment pipeline is:

                   Camera
                     |
                     v
                 PCB Image
                     |
                     v
                Preprocessing
                     |
                     v
                 SAHI Slicing
                     |
                     v
              INT8 ONNX Model
                     |
                     v
                ONNX Runtime
                     |
                     v
                  CPU
                     |
                     v
             Detection Results
                     |
                     v
               AOI Decision

The model can potentially be integrated into an automated inspection system where a camera captures the PCB and the edge device performs inference locally.

This removes the need to continuously send images to a remote server for inference.

---

Edge AI Considerations

Deploying a model on an edge device introduces additional constraints that are usually not important during model training.

For example, a model that works well on a desktop GPU may not be practical on a Raspberry Pi if it requires too much RAM or takes too long to process each image.

Therefore, edge deployment should consider:

Memory

The model must fit comfortably within the available RAM along with the operating system and application.

Storage

A smaller model requires less storage space.

Inference Time

The model must produce predictions quickly enough for the inspection process.

CPU Utilization

The inference workload should not completely saturate the CPU if other parts of the application must run simultaneously.

Power

For embedded systems, lower computational requirements can also help reduce power consumption.

---

Why This Approach?

The project combines three important techniques:

1. YOLO

YOLO provides the object detection capability required to locate PCB defects.

2. INT8 Quantization

INT8 quantization reduces the numerical precision of the model to decrease the model footprint and potentially improve inference efficiency.

3. SAHI

SAHI divides large images into smaller overlapping regions to improve the detection of small objects.

Together, they provide the following architecture:

             YOLO
               |
               v
       INT8 Quantization
               |
               v
             ONNX
               |
               v
             SAHI
               |
               v
        CPU / Edge Device
               |
               v
          PCB AOI System

---

Advantages

The approach provides several advantages for edge deployment:

• Smaller model size
• Reduced storage requirements
• Lower memory footprint
• CPU-oriented inference
• No dedicated GPU required
• Improved handling of small defects using SAHI
• ONNX-based deployment
• Suitable for experimentation on embedded hardware

---

Limitations

The model's performance depends on several factors.

These include:

• Training dataset quality
• Number of training samples
• Image resolution
• Camera quality
• Lighting conditions
• PCB orientation
• Defect size
• Defect appearance
• Confidence threshold
• SAHI slice size
• Slice overlap
• Target hardware

Very small or visually ambiguous defects may still be difficult to detect.

Quantization can also cause a difference in detection accuracy compared with the original FP32 model.

Therefore, the INT8 model should be evaluated on the actual PCB dataset and hardware where it will be deployed.

---

Future Work

The following improvements can be explored in future versions of the project:

• Deployment on Raspberry Pi
• Real-time PCB inspection
• ONNX Runtime benchmarking
• FP32 vs INT8 accuracy comparison
• FP32 vs INT8 inference latency comparison
• RAM usage measurement
• CPU utilization measurement
• Power consumption measurement
• FPS benchmarking
• Hardware-specific acceleration
• Further model compression
• Improved small-object detection
• Camera integration
• Automated pass/fail PCB inspection

---

Deployment Goal

The final goal is to create a complete edge-based PCB inspection system:

             PCB / Camera
                   |
                   v
             Image Capture
                   |
                   v
              Preprocessing
                   |
                   v
              SAHI Slicing
                   |
                   v
           INT8 ONNX Inference
                   |
                   v
             Defect Detection
                   |
                   v
           Detection Processing
                   |
                   v
              AOI Decision
             /           \
            /             \
           v               v
        PASS              FAIL

The important aspect of this project is not only detecting PCB defects, but also investigating how the detection model can be optimized and deployed under real hardware constraints.

---

License

This project is released under the MIT License.

---

Author

Kshitij Hedau

Hugging Face: kshitij1507

---

Citation

If you use this project in your work, please cite:

Kshitij Hedau.
PCB-AOI-Hardware-Constraint.
Hugging Face.