HRNetV2-ONNX

HRNetV2-W48 (ONNX) – Renesas X5H

Introduction

This repository hosts HRNetV2-W48, targeting the Renesas R-Car X5H platform for image-segmentation inference on the NPX6 NPU.

• Model Architecture: HRNetV2 (High-Resolution Network v2, W48 width) with an FCN decode head — extends HRNet by concatenating the upsampled multi-resolution feature maps for dense-prediction tasks such as semantic segmentation
• Source Model: open-mmlab/mmsegmentation
• Task: image-segmentation (dataset: ade20k)
• Note: The upstream mmsegmentation config targets 512x512 crops; the benchmark export used here runs at 512x1024 input resolution.

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

hrnet_v2_seg_sim.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM80 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input: 3 × 512 × 1024

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/HRNetV2-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM80" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)