FCN-Unet-ONNX

FCN-UNet (ONNX) – Renesas X5H

Introduction

This repository hosts FCN-UNet, targeting the Renesas R-Car X5H platform for image-segmentation inference on the NPX6 NPU.

• Model Architecture: U-Net (S5-D16 encoder-decoder) with an FCN decode head — a classic encoder-decoder segmentation architecture with skip connections between symmetric down/up-sampling stages
• Source Model: open-mmlab/mmsegmentation
• Task: image-segmentation (dataset: cityscapes)

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

unet-s5-d16_fcn_4xb4-160k_cityscapes-512x1024.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM80 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input: 3 × 512 × 1024

Accuracy

TBD — not yet measured/published for this repo.

---

Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

---

Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/FCN-Unet-ONNX --repo-type=model --include "fp32/*"

---

Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM80" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)