DeiT3-Small-Patch16-224-ONNX

DeiT III – Small/16 @ 224 (ONNX) – Renesas X5H

Introduction

This repository hosts DeiT III (Small/16, 224px), targeting the Renesas R-Car X5H platform for image classification inference on the NPX6 NPU.

• Model Architecture: DeiT III (Small/16) — a Vision Transformer trained with Meta AI's revised "DeiT III" training recipe (3-Augment data augmentation, LayerScale, stochastic depth), without the distillation token used in the original DeiT
• Source Model: timm/deit3_small_patch16_224.fb_in1k (trained on ImageNet-1k only by the paper authors; a related .fb_in22k_ft_in1k variant also exists, but the compile artifact carries no "in22k" marker, so the plain .fb_in1k checkpoint is the best-supported match)
• Paper: DeiT III: Revenge of the ViT (Touvron, Cord, Jégou, Meta AI, ECCV 2022)
• Task: Image Classification (ImageNet-1k, 1000 classes)
• Parameters: 22.1M (timm model card figure)
• License: Apache-2.0 (per timm model card)

Deployment Flow

The FP32 ONNX model is auto-cast to INT8 by the Renesas MWMX toolchain at compile time — no separate quantization step is required.

deit3_small_patch16_224_Opset18_..._optimized.onnx (FP32)
        │
        └─▶  MWMX Runtime  ──▶  INT8 auto-cast  ──▶  NPX6 NPU

Provided Artifacts

Performance

Measured on Renesas R-Car X5H via the MWMX runtime (APM50 ship-performance CI pipeline).

Benchmark configuration: Single NPU · Batch size: 1 · Input resolution: 224×224 (NCHW 1,3,224,224)

Accuracy

TBD — not yet measured/published for this repo.

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Runtime Details

MWMX Runtime

• Engine: Renesas MWMX (Middleware MX) native inference runtime
• Input format: FP32 ONNX (compiled by the MWMX toolchain)
• NPU execution precision: INT8 (auto-cast by MWMX toolchain)
• Execution target: NPX6-48K NPU on R-Car X5H

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Prerequisites

To run inference on Renesas R-Car X5H, you need:

1. Renesas R-Car X5H board with NPX6 NPU
2. Renesas MWMX Runtime
3. Hugging Face CLI to download the model

Download

hf download Renesas/DeiT3-Small-Patch16-224-ONNX --repo-type=model --include "fp32/*"

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Benchmark Methodology

• HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon via the MWMX runtime (metawaremx_runtime CI pipeline, "APM50" ship-performance target)
• Precision: FP32 ONNX input; INT8 execution (auto-cast by MWMX)
• Slices: only the 1 AI-core slice is available; the 12-core slice was Skipped in the source APM50 CI run for this model